Physical Design Engineer required for SmartPlay, Bangalore

Design Implementation/DFT/Synthesis/STA for SmartPlay (previously TechForce)

Experience: 4-8 yrs

Education: BE / BTech / ME / MTech (electronics )

Designation: Mid Level / Lead

Location: Bangalore

Skills:

• Compression insertion with X-tolerance, ATPG TPI insertion for coverage improvement, Test mode timing analysis with PT-SI, Debugging pattern simulation with timing for ATPG & memory BIST
• Tester handling & bring-up structural vectors, DFT Verification, DFT implementation, Test Compressor, Full chip SOC, ATPG
• Worked on Synthesis ,STA in synopsys flow, FV in synopsys flow, Knowledge of RTL coding, Synthesis of IP’s, Spyglass is an added advantage
• Good at STA,Timing analysis forFull chip at 65nm
• Should have worked on synopsys tool – DC,primetime
• Should have Formal Verification using LEC

Contact: getjobsinindia2007@gmail.com

Embedded Software Engineer required for TechForce, Bangalore

Embedded Software Engineer

Experience: 3 to 5 years

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Job Requirement:

• Experience in Embedded MAC Protocol Stack development (802.16, 802.11, GSM/GPRS)
• RTOS based software development (VxWorks, PSOS, Embedded Linux)
• Experience in embedded SW development tools
• Experience in developing Networking/Protocol Stack Software for Modems, Access Points
• Experience in testing communication protocols, Wireless terminals, Base Stations
• Experience writing device drivers on PC and embedded platforms (Linux)
• Strong RTOS kernel and RTOS driver development experience
• Experience in working with wireless, networking, USB stacks

Contact: getjobsinindia2007@gmail.com

SoC Physical Design Engineer required for TechForce, Bangalore

SoC Physical Design Engineer

Experience: 3+ years

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Job Requirement:

• Implementation of multimillion gate SoC designs in cutting edge process technologies (130nm, 90nm & 65nm)
• Work on all aspects of physical design including synthesis, floor planning, bond out, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout
• Clear understanding and command over all aspects of physical design
• Experience in ASIC tapeouts, preferably in 90nm or smaller technology technologies
• Expertise in Synopsys, Magma or Cadence backend tools
• Skill and experience in scripting using Tcl or Perl desirable

Contact: getjobsinindia2007@gmail.com

Custom Layout Lead Engineer is required for TechForce, Bangalore

Custom Layout Lead Engineer

Experience: 8 to 10 years of experience in design and layout of memories and standard cells

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Responsibilities:

• Hands-on Lead engineer involved in execution and management of Memory, Standard Cell and other Custom layout projects
• Actively interface with the customer and the engineering team and ensure timely delivery of projects
• Train, mentor & manage the junior engineers
• Job involves execution of work at customer site and at TechForce design center
• May have to travel outside India for a brief period of time customer meetings, project kickoff meetings etc.

Job Requirement:

• Experience in Spice Simulation, Circuit Design, good understanding of memory architecture
• Excellent verbal and written communication skills
• Well experienced is using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Ability to lead the engineering team

Contact: getjobsinindia2007@gmail.com

SoC Design Verification Engineer required for TechForce, Bangalore

SoC Design Verification Engineer

Experience: 3+ years

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Job Requirement:

• Expertise in Verilog, VHDL
• Proficiency in one or more HVL's a must (Vera, Specman, System C, System Verilog, C/C++)
• Domains – Wireless, Wimax, Graphics, Multimedia, Networking, PCI Express, USB experience a plus
• Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
• Knowledge of Functional coverage using HVL language features or assertions a plus
• Microcode Development
• Good Debugging Skills

Contact: getjobsinindia2007@gmail.com

Physical Design Engineer required for TechForce, Bangalore

Physical Design Engineers, Bangalore

Skills:

• Tools - Synopsys, Cadence, Magma tools
• Technologies – 45nm, 65nm or 90nm

Location: Hyderabad

Experience: 3 - 15 years experience (from Junior level to Sr Technical Lead Position)

Education: BE / MS / M Tech

Job Requirements:

• Minimum 3 year of ASIC physical design experience.
• Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
• Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
• Should have participated in a minimum of 3-4 fullchip tapeouts.
• Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
• Familiar with Physical Verification will be a plus.

In addition, following is desirable:

• Effective written and oral communication skills in English
• Understanding Verilog HDL
• Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Fullchip level Timing closure skills
• Displaying motivation, leadership skills and working in teams

Responsibilities:

• Will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks. In addition to this, will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.

Contact: getjobsinindia2007@gmail.com

Senior Verification Engineer required for TechForce Design Services

Senior Verification Engineer - Bangalore

Skills/Expertise:

• Language: Vera, System Verilog, System C, Verilog, VHDL
• Domain: USB, PCI, PCI express, ARM, AMBA, Storage or Any peripherals

Location: Bangalore

Experience: 4 yrs & above

Education: BE / B.Tech / ME / MTech / MS

Qualification:

• Expertise in either Vera language or mentioned domain expertise will be preferred
• Exposure to gate level simulation (ModelSim)
• Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
• Knowledge of Functional coverage using HVL language features or assertions a plus
• Proficiency in developing testcases and testbench environment.

Contact: getjobsinindia2007@gmail.com

Senior Verification Engineer required for TechForce Design Services

Senior Verification Engineer - Hyderabad

Skills/Expertise:

• Languages: Vera, System Verilog, Verilog
• Domains preferred: MPEG, MP3, Multimedia, Audio, Video

Location: Hyderabad

Experience: 4 yrs & above

Education: BE / B.Tech / ME / MTech / MS

Qualification:

• Expertise in either mentioned languages or mentioned domain expertise will be preferred
• Exposure to gate level simulation (ModelSim)
• Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
• Knowledge of Functional coverage using HVL language features or assertions a plus
• Proficiency in developing testcases and testbench environment.

Contact: getjobsinindia2007@gmail.com

ASIC Verification Engineer required for TechForce Design Services

ASIC Verification Engineer - Noida

Skills/Expertise:

• Languages: Verilog / VHDL / Specman / Vera / System Verilog / System C
• Location: Noida

Experience: 2 yrs – 8 yrs

Education: BE / B.Tech / ME / MTech / MS

Qualification:

• Experience in Verilog / VHDL / Specman / Vera / System Verilog / System C
• Exposure to gate level simulation (ModelSim)
• Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc
• Knowledge of Functional coverage using HVL language features or assertions a plus
  Proficiency in developing testcases and testbench environment.

Important Note: Free accommodation will be provided by us in Noida city until the project is completed for the selected engineers.

Contact: getjobsinindia2007@gmail.com

ASIC Verification Engineer (Specman) required for TechForce Design Services

ASIC Verification Engineer – Noida (Specman)

Skills/Expertise:

• Languages: Specman “e”
• IP verification preferred

Location: Noida

Experience: 2 yrs – 8 yrs

Education: B.E. / B.Tech / ME / MTech / MS

Qualification:

• Experience in test bench development in Specman
• Experience in IP verification preferred
• Experience in writing the test cases with decent debugging skills.

Important Note: Free accommodation will be provided by us in Noida city until the project is completed for the selected engineers.

Contact: getjobsinindia2007@gmail.com

Physical Design Engineer for TechForce Design Services

Physical Design Engineer

Skill/Expertise:

• Tools: Magma / Cadence / Astro
• Experience: 2 - 8 years
• Location: Hyderabad & Noida
• Education: BE – EE/EC/ET/EI

Job Description/Responsibilities:

• Implementation of multimillion gate SoC designs in cutting edge process technologies (130nm, 90nm & 65nm)
• Will be working on all aspects of physical design including synthesis, floor planning, bond out, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, formal verification, DFM, and tapeout.
• Meeting highly challenging schedule, performance, and quality constraints.

Candidate profile:

• Clear understanding and command over all aspects of physical design including technology, libraries, floorplan, timing, signal integrity and power dissipation.
• Experience in ASIC tapeouts, preferably in 130nm or smaller technology nodes
• Expertise in Cadence/Magma/Astro backend tools
• Skill and experience in scripting using Tcl or Perl desirable
• Demonstrated ability to work in a team environment

Contact: getjobsinindia2007@gmail.com