Physical Design Engineer required for SmartPlay, Bangalore

Design Implementation/DFT/Synthesis/STA for SmartPlay (previously TechForce)

Experience: 4-8 yrs

Education: BE / BTech / ME / MTech (electronics )

Designation: Mid Level / Lead

Location: Bangalore

Skills:

• Compression insertion with X-tolerance, ATPG TPI insertion for coverage improvement, Test mode timing analysis with PT-SI, Debugging pattern simulation with timing for ATPG & memory BIST
• Tester handling & bring-up structural vectors, DFT Verification, DFT implementation, Test Compressor, Full chip SOC, ATPG
• Worked on Synthesis ,STA in synopsys flow, FV in synopsys flow, Knowledge of RTL coding, Synthesis of IP’s, Spyglass is an added advantage
• Good at STA,Timing analysis forFull chip at 65nm
• Should have worked on synopsys tool – DC,primetime
• Should have Formal Verification using LEC

Contact: getjobsinindia2007@gmail.com