PDK engineers required for Cadence Design Systems, Bangalore

Process Development Kit (PDK) Engineer as Lead/Senior Services AE

Experience: 3 to 8 years

Education: BE / BTech / ME / MTech

Location: Bangalore

Job description:

• This engineer’s primary role will be to work in a team oriented environment to create, customize and maintain Process Design Kits (PDKS) for Cadence technology.

• He/she will interact and work with other engineers on the worldwide PDK delivery team.
  

Responsibilities:

• Understanding and interpreting integrated circuit process technologies in order to implement specifications for Cadence optimized Process Design Kits (PDKs).
• Development and maintenance of PDKs includes creation of techfiles, symbols, PCells, Call Backs, CDFs, netlisting and the creation of Qualification data.
• Proficient with the use of PDK automation tools is a plus.
• The engineer must have a solid background in circuits, electronics and physics and should either have or be capable of learning new technical and consulting skills.
• The candidate should possess the necessary engineering and/or consultancy skills, i.e. that he/she is technically excellent with mature communication skills to be able to consult effectively with clients, e.g. to communicate with Customers.
• Contribute to training activities

Requirements:

• Execution on VCAD Customer support projects, e.g. Implementation and testing of PDKs, their components, methodology support, operation and maintenance of VCAD design environments.
• Design Support in VCAD Customer Design projects, both remotely and onsite.
• VCAD Methodology Service Engagements, e.g. Implementation and testing of PDKs, methodology development, operation and maintenance of VCAD design environments.
• Ability to undertake design environment implementation tasks alone and architectural tasks with support within the first year.
• Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires good communication skills in English.
• Acquire a basic understanding of the (service) business environment of Cadence within 1 month including pre sales support.

Contact: getjobsinindia2007@gmail.com

Sr. Technical Writer required for Cadence Design Systems, NOIDA

Sr. Technical Writer

Experience: 3+ yrs

Education: BE / BTech / ME / MTech

Location: NOIDA

Skills:

• Ability to comprehend technical concepts with experience in creating end-user and system-level documentation and help systems for complex software
• Thorough knowledge of technical writing concepts
• An excellent command over English, with good editing and proof-reading skills
• Proficiency in FrameMaker, Webworks, and MS-Office tools
• Electronics/EDA experience preferred but not mandatory
  

Contact: getjobsinindia2007@gmail.com

Sr. Support AE required for Cadence Design Systems, NOIDA

Sr. Support AE

Experience: 3-8 yrs

Education: BE / BTech / ME / MTech

Designation: Mid Level / Lead

Location: NOIDA

Job Description:

• The Support Applications Engineer (AE) will provide direct technical customer support for Cadence products and will focus on applying technical expertise in multiple products within a specific technology family.
• The person should be able to act as strong team member and contributor, participate in team projects and initiatives.
• Expertise in OrCAD Capture, ConceptHDL and Allegro PCB Editor, are added advantage.
• The person should possess team-success orientation, mature work attitude, and good judgment under pressure.

Responsibilities:

• Provide technical support to customers, internal and external, for Cadence's Allegro PCB Editor, Allegro Design Entry
• Provide installation and licensing help
• Advocate and negotiate bug/enhancement resolution with R&D
• Contribute to and/or lead internal technology rollout projects and training
• Develop solutions for inclusion in the Cadence knowledge database

Skills:

• Experience on any Allegro Design Entry HDL (Concept HDL), Allegro PCB Editor, spectra and Allegro Package Design or equivalent competitor tools
• Knowledge of High speed design, Signal Integrity and packaging will be an added advantage
• Possess sound, basic knowledge of EDA industry, R&D Technology Roadmaps, and design flows within own area of technical expertise

Contact: getjobsinindia2007@gmail.com

Physical Design Engineer required for SmartPlay, Bangalore

Design Implementation/DFT/Synthesis/STA for SmartPlay (previously TechForce)

Experience: 4-8 yrs

Education: BE / BTech / ME / MTech (electronics )

Designation: Mid Level / Lead

Location: Bangalore

Skills:

• Compression insertion with X-tolerance, ATPG TPI insertion for coverage improvement, Test mode timing analysis with PT-SI, Debugging pattern simulation with timing for ATPG & memory BIST
• Tester handling & bring-up structural vectors, DFT Verification, DFT implementation, Test Compressor, Full chip SOC, ATPG
• Worked on Synthesis ,STA in synopsys flow, FV in synopsys flow, Knowledge of RTL coding, Synthesis of IP’s, Spyglass is an added advantage
• Good at STA,Timing analysis forFull chip at 65nm
• Should have worked on synopsys tool – DC,primetime
• Should have Formal Verification using LEC

Contact: getjobsinindia2007@gmail.com

Custom Layout Lead Engineer is required for TechForce, Bangalore

Custom Layout Lead Engineer

Experience: 8 to 10 years of experience in design and layout of memories and standard cells

Locaiton: Bangalore

No. of Positions: 1

Education: BE/BTech or ME/MTech

Responsibilities:

• Hands-on Lead engineer involved in execution and management of Memory, Standard Cell and other Custom layout projects
• Actively interface with the customer and the engineering team and ensure timely delivery of projects
• Train, mentor & manage the junior engineers
• Job involves execution of work at customer site and at TechForce design center
• May have to travel outside India for a brief period of time customer meetings, project kickoff meetings etc.

Job Requirement:

• Experience in Spice Simulation, Circuit Design, good understanding of memory architecture
• Excellent verbal and written communication skills
• Well experienced is using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Ability to lead the engineering team

Contact: getjobsinindia2007@gmail.com

Senior Services Applicaiton Engineer (DFT) required for Cadence Design Systems, Bangalore

Experience: 3 to 5 years

Location: Bangalore

No. of Positions: 1

Job Requirement:

• All phases of DFT implementation and analysis (Scan, ATPG, BIST, JTAG)
• Post-silicon debugging exposure
• Professional experience in Synthesis
• Prior knowledge on Conformal/Formal Verification activitie

Contact: getjobsinindia2007@gmail.com

Sr. Technical Writer required for Cadence Design Systems, Noida

Experience: 4 to 10 yrs

Location: Noida, India

No. of Positions: 1

Job Requirement:

• Experience in writing user manuals, reference manuals a must
• Excellent English, with good editing and proof reading skills.
• Proficiency in FrameMaker, Webworks, and MS-Office tools

Contact: getjobsinindia2007@gmail.com

Member of Consulting Staff required for Cadence Design Systems, Noida

Experience: 4 to 8 years

Location: Noida, India

No. of Positions: 1

Job Requirement:

• Should be proficient in synthesis ( worked on block level synthesis using DC and RC) as well as good in LEC, CCD and Low power design area.
• Should be good in Tcl, Perl and Shell scripting also

Contact: getjobsinindia2007@gmail.com

Physical Design Engineer required for TechForce, Bangalore

Physical Design Engineers, Bangalore

Skills:

• Tools - Synopsys, Cadence, Magma tools
• Technologies – 45nm, 65nm or 90nm

Location: Hyderabad

Experience: 3 - 15 years experience (from Junior level to Sr Technical Lead Position)

Education: BE / MS / M Tech

Job Requirements:

• Minimum 3 year of ASIC physical design experience.
• Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
• Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
• Should have participated in a minimum of 3-4 fullchip tapeouts.
• Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
• Familiar with Physical Verification will be a plus.

In addition, following is desirable:

• Effective written and oral communication skills in English
• Understanding Verilog HDL
• Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Fullchip level Timing closure skills
• Displaying motivation, leadership skills and working in teams

Responsibilities:

• Will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks. In addition to this, will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.

Contact: getjobsinindia2007@gmail.com