tag:blogger.com,1999:blog-37384341497602844172024-03-13T10:43:27.715-07:00Jobs in IndiaSandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.comBlogger47125tag:blogger.com,1999:blog-3738434149760284417.post-23462377487056241532010-02-09T21:54:00.000-08:002010-02-09T22:02:39.267-08:00Silicon Validation Engineers required for KPIT Cummins, Bangalore<div style="text-align: left;"><span style="font-weight: bold;">Silicon Validation Enginee</span><span style="font-weight: bold;">rs</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 3 to 5 years<br /><br /><span style="font-weight: bold;"><u>No. of Positions:</u></span> 6<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Bangalore<br /><p><span style="font-weight: bold;"><u>Job description:</u></span></p><ul><li>Develop validation scripts/drivers for the validation of hardware modules in the SOC</li><li>Create validation specifications</li><li>Run the SOC validation tests, Capture the observations and generate validation test reports</li><li>Identify the bugs in silicon,<br /></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-35096573491974006482010-02-05T02:33:00.000-08:002010-02-05T02:45:08.818-08:00PDK engineers required for Cadence Design Systems, Bangalore<div style="text-align: left;"><span style="font-weight: bold;">Process Development Kit (PDK) Engineer</span> as <span style="font-weight: bold;">Lead/Senior Services AE</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 3 to 8 years<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Bangalore<br /><p><span style="font-weight: bold;"><u>Job description:</u></span></p><ul><li>This engineer’s primary role will be to work in a team oriented environment to create, customize and maintain Process Design Kits (PDKS) for Cadence technology.</li></ul><ul><li>He/she will interact and work with other engineers on the worldwide PDK delivery team.<br /></li></ul><p><span style="font-weight: bold;"><u>Responsibilities:</u></span><br /></p><ul><li>Understanding and interpreting integrated circuit process technologies in order to implement specifications for Cadence optimized Process Design Kits (PDKs). </li><li>Development and maintenance of PDKs includes creation of techfiles, symbols, PCells, Call Backs, CDFs, netlisting and the creation of Qualification data. </li><li>Proficient with the use of PDK automation tools is a plus. </li><li>The engineer must have a solid background in circuits, electronics and physics and should either have or be capable of learning new technical and consulting skills. </li><li>The candidate should possess the necessary engineering and/or consultancy skills, i.e. that he/she is technically excellent with mature communication skills to be able to consult effectively with clients, e.g. to communicate with Customers. </li><li>Contribute to training activities</li></ul><p><span style="font-weight: bold;"><u>Requirements:</u></span><br /></p><ul><li>Execution on VCAD Customer support projects, e.g. Implementation and testing of PDKs, their components, methodology support, operation and maintenance of VCAD design environments. </li><li>Design Support in VCAD Customer Design projects, both remotely and onsite. </li><li>VCAD Methodology Service Engagements, e.g. Implementation and testing of PDKs, methodology development, operation and maintenance of VCAD design environments. </li><li>Ability to undertake design environment implementation tasks alone and architectural tasks with support within the first year. </li><li>Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires good communication skills in English. </li><li>Acquire a basic understanding of the (service) business environment of Cadence within 1 month including pre sales support.</li></ul><p></p></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com2tag:blogger.com,1999:blog-3738434149760284417.post-15321821823214680952010-02-02T22:47:00.000-08:002010-02-02T22:49:27.407-08:00C++ Developers required for Cadence Design Systems, NOIDA<div style="text-align: left;"><span style="font-weight: bold;">C++ Developers</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 7+ yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> NOIDA<br /><p><span style="font-weight: bold;"><u>Skills:</u></span></p><ul><li>An excellent command in C and C++ programming<br /></li><li><span>Electronics/EDA experience<br /></span></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-30131769321879159362009-06-30T06:45:00.000-07:002009-06-30T06:48:40.473-07:00Technical Education Services Engineer required for Cadence Design Systems, NOIDA / Bangalore<div style="text-align: left;"><span style="font-weight: bold;">Technical Education Services Engineer</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 3-5 yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> NOIDA/Bangalore<br /><p><span style="font-weight: bold;"><u>Skills:</u></span></p><ul><li><span>Practical knowledge of model development in spice, verilog, verilog-a and vhdl</span></li><li><span>Solid understanding of CMOS analog circuit design techniques and circuit layout considerations</span></li><li><span>Experience in simulation/validation of mixed signal ASIC’s</span></li><li><span>Hands on development of analog/mixed signal flows and methodologies</span></li><li><span>Proficiency in the following front end CAD tools</span></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com2tag:blogger.com,1999:blog-3738434149760284417.post-46962609513076640632009-06-30T06:03:00.000-07:002009-06-30T06:45:29.211-07:00Configuration Management Engineer required for Cadence Design Systems, NOIDA<div style="text-align: left;"><span style="font-weight: bold;">Configuration Management Engineer</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 3-7 yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> NOIDA<br /><p><span style="font-weight: bold;"><u>Skills:</u></span></p><ul><li><span>Experience of working on the UNIX platform and usage of a Version Control tool like CVS is a must and Knowledge of PERL and UNIX shell scripting is a plus</span></li><li>Candidate should be familiar with MAKE, and compilation process</li><li>CVS experience is a strong match</li><li>Work experience in multi-team, multi-sited projects is a plus</li><li>Experience in working with computing clusters/ server farms/ grid computing is a definite plus<span><br /></span></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-63746591037137304752009-06-30T05:55:00.000-07:002009-06-30T05:59:14.086-07:00Sr. Technical Writer required for Cadence Design Systems, NOIDA<div style="text-align: left;"><span style="font-weight: bold;">Sr. Technical Writer</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 3+ yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> NOIDA<br /><p><span style="font-weight: bold;"><u>Skills:</u></span></p><p></p><ul><li><span>Ability to comprehend technical concepts with experience in creating end-user and system-level documentation and help systems for complex software</span></li><li>Thorough knowledge of technical writing concepts</li><li>An excellent command over English, with good editing and proof-reading skills</li><li>Proficiency in FrameMaker, Webworks, and MS-Office tools</li><li><span>Electronics/EDA experience preferred but not mandatory<br /></span></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-61430115458467613212009-06-30T05:49:00.000-07:002009-06-30T06:02:05.359-07:00Project Lead required for Cadence Design Systems, NOIDA<div style="text-align: left;"><span style="font-weight: bold;">Project Lead</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 7-10 yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> NOIDA<br /><p><strong><u>Job Description</u></strong><span class="pc-rtg-h2">: </span><br /></p><ul><li><span class="pc-rtg-body">Manages the planning, development, and implementation of procedures for the testing and evaluation of support website</span></li><li><span class="pc-rtg-body">Specifies tests to be performed, compiles data, and makes recommendations for changes required in testing procedures, processes, new testing requirements and/or design of testing environment</span></li><li><span class="pc-rtg-body">Selects, develops, and evaluates personnel to ensure the efficient operation of the function</span></li><li><span class="pc-rtg-body">Receives assignments in the form of objectives with goals and the process by which to meet goals</span></li><li><span class="pc-rtg-body">Management reviews work to measure meeting of objectives</span></li><li><span class="pc-rtg-body">Works on issues where analysis of situation or data requires review of relevant factors</span></li><li><span class="pc-rtg-body">Exercises judgment within defined procedures and policies to determine appropriate action</span></li><li><span class="pc-rtg-body">Erroneous decisions or failure to achieve results will cause delays in schedules</span></li><li><span class="pc-rtg-body">Frequently interacts with functional peer groups. </span></li></ul><p><strong><u>Technical Experience</u></strong><span class="pc-rtg-h2">:</span><br /><span class="pc-rtg-body"></span></p><ul><li><span class="pc-rtg-body">MS Office</span></li><li><span class="pc-rtg-body">MS Project</span></li><li><span class="pc-rtg-body">Website administration</span><br /></li></ul><p><strong><u>Soft Skills</u></strong><span class="pc-rtg-h2">:</span><span class="pc-rtg-body"><br /></span></p><ul><li><span class="pc-rtg-body">Demonstrated ability to lead distributed project teams</span></li><li><span class="pc-rtg-body">Ability to gain cooperation of others</span></li><li><span class="pc-rtg-body">Experience in conducting presentations of technical information concerning specific projects or schedules</span><br /></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-91629832203944248292009-06-30T05:41:00.000-07:002009-06-30T05:49:01.161-07:00Project Manager required for Cadence Design Systems, NOIDA<div style="text-align: left;"><span style="font-weight: bold;"></span><span style="font-weight: bold;">Project Manager</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 7-10 yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech<br /><br /><span style="font-weight: bold;"><u></u></span><span style="font-weight: bold;"><u>Location:</u></span> NOIDA<br /><p><span style="font-weight: bold;"><u>Job Description:</u></span><span class="pc-rtg-h2"></span><br /></p><ul><li><span class="pc-rtg-body">Project manager for project-based timecard system.</span></li><li>Business owner responsible for routine monitoring to ensure the system is operating efficiently, entry and business prioritization of occasional upgrades/improvements to the system per end-user demand, and yearly system upgrades at the beginning of each year.<br /></li><li>Must have broad-based proficiency in SAP including but not limited to: creation and deletion of cost centers and work centers, mass upload of labor rates, expenditure reports, cost center reports, ww labor rate reports, removal or changing of employee hours, project creation and update, timecard noncompliance and numerous other profiles. Responsible for generation of time management reports as well as weekly/quarterly Excel-based timecard analysis for worldwide internal customer base.</li><li>Requires the ability to work cross functionally and respond to worldwide user base.<br /></li></ul><p><span style="font-weight: bold;"><u>Technical Experience:</u></span><br /></p><ul><li><span class="pc-rtg-body">Substantial expertise with SAP (PF1, PR1, HRP-HCM) focused on Finance/Project Accounting/HR</span></li><li><span class="pc-rtg-body">Experience with electronic timecard systems</span></li><li><span class="pc-rtg-body">Deep expertise in MS Excel (merging multiple databases, writing and debugging VBE macros, usage of pivot tables)</span></li><li><span class="pc-rtg-body">Demonstrated project management experience</span></li></ul><span style="font-weight: bold;"><u>Soft Skills:</u></span><ul><li><span class="pc-rtg-body"></span><span class="pc-rtg-body">Demonstrated ability to quickly resolve unusual user issues & demands</span></li><li><span class="pc-rtg-body">Ability to work an extensive work schedule during quarterly and yearly closing periods in a global environment</span></li><li><span class="pc-rtg-body">Strong command of spoken English. </span></li></ul></div><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-4891037796381466552009-06-30T05:25:00.000-07:002009-06-30T05:41:32.564-07:00Sr. Support AE required for Cadence Design Systems, NOIDA<div style="text-align: left;"><span style="font-weight: bold;">Sr. Support AE</span><br /><br /><span style="font-weight: bold;"><u></u></span><span style="font-weight: bold;"><u>Experience:</u></span> 3-8 yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech<br /><br /><span style="font-weight: bold;"><u>Designation:</u></span> Mid Level / Lead<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> NOIDA<br /><br /><span style="text-decoration: underline;"><span style="font-weight: bold;">Job Description:<br /></span></span> <ul><li><span class="pc-rtg-body">The Support Applications Engineer (AE) will provide direct technical customer support for Cadence products and will focus on applying technical expertise in multiple products within a specific technology family.</span></li><li><span class="pc-rtg-body">The person should be able to act as strong team member and contributor, participate in team projects and initiatives.</span></li><li><span class="pc-rtg-body">Expertise in OrCAD Capture, ConceptHDL and Allegro PCB Editor, are added advantage. </span></li><li><span class="pc-rtg-body">The person should possess team-success orientation, mature work attitude, and good judgment under pressure.</span></li></ul><p><span style="text-decoration: underline;"><span style="font-weight: bold;">Responsibilities</span></span><span style="font-weight: bold;"><u>:</u></span><span class="pc-rtg-body"><span style="font-weight: bold;"></span><br /></span></p><ul><li><span class="pc-rtg-body">Provide technical support to customers, internal and external, for Cadence's Allegro PCB Editor, Allegro Design Entry</span></li><li><span class="pc-rtg-body">Provide installation and licensing help</span></li><li><span class="pc-rtg-body">Advocate and negotiate bug/enhancement resolution with R&D</span></li><li><span class="pc-rtg-body">Contribute to and/or lead internal technology rollout projects and training</span></li><li><span class="pc-rtg-body">Develop solutions for inclusion in the Cadence knowledge database</span></li></ul><span style="font-weight: bold;"><u></u></span><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span><span style="font-weight: bold;"><u></u></span><span style="font-weight: bold;"><u>Skills:</u></span><br /></div><span></span><ul><li><span>Experience on any Allegro Design Entry HDL (Concept HDL), Allegro PCB Editor, spectra and Allegro Package Design or equivalent competitor tools</span></li><li><span>Knowledge of High speed design, Signal Integrity and packaging will be an added advantage</span></li><li><span>Possess sound, basic knowledge of EDA industry, R&D Technology Roadmaps, and design flows within own area of technical expertise</span></li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com1tag:blogger.com,1999:blog-3738434149760284417.post-84543659032530277642009-06-22T01:01:00.000-07:002009-06-22T04:40:45.781-07:00Physical Design Engineer required for SmartPlay, Bangalore<div style="text-align: left;"><span style="font-weight: bold;">Design Implementation/DFT/Synthesis/STA</span> <span style="font-weight: bold;">for </span><a style="font-weight: bold;" href="http://www.smartplayin.com/">SmartPlay</a><span style="font-weight: bold;"> (previously TechForce)</span><br /><br /><span style="font-weight: bold;"><u>Experience:</u></span> 4-8 yrs<br /><br /><span style="font-weight: bold;"><u>Education:</u></span> BE / BTech / ME / MTech (electronics )<br /><br /><span style="font-weight: bold;"><u>Designation:</u></span> Mid Level / Lead<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Bangalore<br /><br /><span style="font-weight: bold;"><u>Skills:</u></span><br /></span></div><ul style="text-align: left;"><li>Compression insertion with X-tolerance, ATPG TPI insertion for coverage improvement, Test mode timing analysis with PT-SI, Debugging pattern simulation with timing for ATPG & memory BIST</li><li>Tester handling & bring-up structural vectors, DFT Verification, DFT implementation, Test Compressor, Full chip SOC, ATPG</li><li>Worked on Synthesis ,STA in synopsys flow, FV in synopsys flow, Knowledge of RTL coding, Synthesis of IP’s, Spyglass is an added advantage</li><li>Good at STA,Timing analysis forFull chip at 65nm</li><li>Should have worked on synopsys tool – DC,primetime</li><li>Should have Formal Verification using LEC</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-85517131592164570332009-05-02T06:46:00.000-07:002009-05-02T06:49:36.244-07:00Embedded Software Engineer required for TechForce, Bangalore<strong>Embedded Software Engineer</strong><br /><strong><u></u></strong><br /><span style="FONT-WEIGHT: bold"><u>Experience:</u></span> 3 to 5 years<br /><br /><span style="FONT-WEIGHT: bold"><u>Locaiton:</u></span> Bangalore<br /><br /><span style="FONT-WEIGHT: bold"><u>No. of Positions:</u></span> 1<br /><br /><strong><u>Education:</u></strong> BE/BTech or ME/MTech<br /><br /><span style="FONT-WEIGHT: bold"><u>Job Requirement:</u></span><br /><ul><li>Experience in Embedded MAC Protocol Stack development (802.16, 802.11, GSM/GPRS)</li><li>RTOS based software development (VxWorks, PSOS, Embedded Linux)</li><li>Experience in embedded SW development tools</li><li>Experience in developing Networking/Protocol Stack Software for Modems, Access Points</li><li>Experience in testing communication protocols, Wireless terminals, Base Stations</li><li>Experience writing device drivers on PC and embedded platforms (Linux)</li><li>Strong RTOS kernel and RTOS driver development experience</li><li>Experience in working with wireless, networking, USB stacks</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-449074030691713612009-05-02T06:41:00.000-07:002009-05-02T06:45:18.411-07:00SoC Physical Design Engineer required for TechForce, Bangalore<span style="FONT-WEIGHT: bold">SoC Physical Design Engineer</span><br /><strong></strong><br /><span style="FONT-WEIGHT: bold"><u>Experience:</u></span> 3+ years<br /><br /><span style="FONT-WEIGHT: bold"><u>Locaiton:</u></span> Bangalore<br /><br /><span style="FONT-WEIGHT: bold"><u>No. of Positions:</u></span> 1<br /><br /><strong><u>Education:</u></strong> BE/BTech or ME/MTech<br /><br /><span style="FONT-WEIGHT: bold"><u>Job Requirement:</u></span><br /><strong><u></u></strong><ul><li>Implementation of multimillion gate SoC designs in cutting edge process technologies (130nm, 90nm & 65nm)</li><li>Work on all aspects of physical design including synthesis, floor planning, bond out, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout</li><li>Clear understanding and command over all aspects of physical design</li><li>Experience in ASIC tapeouts, preferably in 90nm or smaller technology technologies</li><li>Expertise in Synopsys, Magma or Cadence backend tools</li><li>Skill and experience in scripting using Tcl or Perl desirable</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-24168717171526364772009-05-02T04:45:00.000-07:002009-05-02T06:40:03.105-07:00Custom Layout Lead Engineer is required for TechForce, Bangalore<span style="FONT-WEIGHT: bold">Custom Layout</span> <strong>Lead Engineer</strong><br /><br /><span style="FONT-WEIGHT: bold"><u>Experience:</u></span> 8 to 10 years of experience in design and layout of memories and standard cells<br /><br /><span style="FONT-WEIGHT: bold"><u>Locaiton:</u></span> Bangalore<br /><br /><span style="FONT-WEIGHT: bold"><u>No. of Positions:</u></span> 1<br /><br /><strong><u>Education:</u></strong> BE/BTech or ME/MTech<br /><br /><strong><u></u></strong><strong><u>Responsibilities</u>:</strong><br /><ul><li>Hands-on Lead engineer involved in execution and management of Memory, Standard Cell and other Custom layout projects</li><li>Actively interface with the customer and the engineering team and ensure timely delivery of projects</li><li>Train, mentor & manage the junior engineers</li><li>Job involves execution of work at customer site and at TechForce design center</li><li>May have to travel outside India for a brief period of time customer meetings, project kickoff meetings etc.</li></ul><p><span style="FONT-WEIGHT: bold"><u>Job Requirement:</u></span> </p><ul><li>Experience in Spice Simulation, Circuit Design, good understanding of memory architecture</li><li>Excellent verbal and written communication skills</li><li>Well experienced is using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.</li><li>Ability to lead the engineering team</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-57435202168533508372009-05-02T04:26:00.000-07:002009-05-02T04:43:04.483-07:00SoC Design Verification Engineer required for TechForce, Bangalore<span style="FONT-WEIGHT: bold">SoC Design Verification Engineer</span><br /><strong><u></u></strong><br /><span style="FONT-WEIGHT: bold"><u>Experience:</u></span> 3+ years<br /><br /><span style="FONT-WEIGHT: bold"><u>Locaiton:</u></span> Bangalore<br /><br /><span style="FONT-WEIGHT: bold"><u>No. of Positions:</u></span> 1<br /><br /><strong><u>Education:</u></strong> BE/BTech or ME/MTech<br /><br /><span style="FONT-WEIGHT: bold"><u>Job Requirement:</u></span><br /><ul><li>Expertise in Verilog, VHDL</li><li>Proficiency in one or more HVL's a must (Vera, Specman, System C, System Verilog, C/C++)</li><li>Domains – Wireless, Wimax, Graphics, Multimedia, Networking, PCI Express, USB experience a plus</li><li>Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc</li><li>Knowledge of Functional coverage using HVL language features or assertions a plus</li><li>Microcode Development</li><li>Good Debugging Skills</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-74456744845635753682008-12-16T22:43:00.000-08:002008-12-16T22:47:19.434-08:00Finance Executive (Consultant) required for Cadence Design Systems, Noida<span style="font-weight: bold;"><u>Experience:</u></span> 1 to 5 years<br /><br /><span style="font-weight: bold;"><u>Locaiton:</u></span> Noida<br /><br /><span style="font-weight: bold;"><u>No. of Positions:</u></span> 1<br /><br /><span style="font-weight: bold;"><u>Job Requirement:</u></span><br /><ul><li>Handling Payroll </li><li>T & E Accounting </li><li>General Accounting </li><li>Background in Commerce</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-65401068792602862212008-12-16T22:37:00.000-08:002008-12-16T22:42:56.504-08:00Senior Services Applicaiton Engineer (DFT) required for Cadence Design Systems, Bangalore<span style="font-weight: bold;"><u>Experience:</u></span> 3 to 5 years<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Bangalore<br /><br /><span style="font-weight: bold;"><u>No. of Positions:</u></span> 1<br /><br /><span style="font-weight: bold;"><u>Job Requirement:</u></span><br /><ul><li>All phases of DFT implementation and analysis (Scan, ATPG, BIST, JTAG) </li><li>Post-silicon debugging exposure </li><li>Professional experience in Synthesis </li><li>Prior knowledge on Conformal/Formal Verification activitie</li></ul><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-88593813512001082712008-12-16T22:32:00.000-08:002008-12-16T22:37:14.451-08:00Sr. Technical Writer required for Cadence Design Systems, Noida<span style="font-weight: bold;"><u>Experience:</u></span> 4 to 10 yrs<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Noida, India<br /><br /><span style="font-weight: bold;"><u>No. of Positions:</u></span></u> 1<br /><br /><span style="font-weight: bold;"><u>Job Requirement:</u></span><br /><ul><li>Experience in writing user manuals, reference manuals a must </li><li>Excellent English, with good editing and proof reading skills. </li><li>Proficiency in FrameMaker, Webworks, and MS-Office tools</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-64363592759056901002008-12-16T21:50:00.000-08:002008-12-16T22:31:09.869-08:00Member of Consulting Staff required for Cadence Design Systems, Noida<span style="font-weight: bold;"><u>Experience:</u></span> 4 to 8 years<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Noida, India<br /><br /><span style="font-weight: bold;"><u>No. of Positions:</u></span> 1<br /><br /><span style="font-weight: bold;"><u>Job Requirement:</u></span><br /><ul><li>Should be proficient in synthesis ( worked on block level synthesis using DC and RC) as well as good in LEC, CCD and Low power design area. </li><li>Should be good in Tcl, Perl and Shell scripting also</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-63748318261826812382008-10-15T00:12:00.000-07:002008-10-15T00:13:11.568-07:00Verification Engineer required for Cadence Design Systems, Bangalore or Noida<span style="font-weight: bold;"><u>Experience:</u></span> 4 to 5 years<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> India, Bangalore or Noida<br /><br /><span style="font-weight: bold;"><u>Job Requirement:</u></span><br /><ul><li>This engineer’s primary role will be to work in a team oriented environment to deliver digital logic design and verification methodologies, customised design environments and design implementation solutions that align with client goals. He/she will interact and work with other engineers on the worldwide D&V VCAD delivery team. </li><li>Responsibilities will include creating and customising design environments, design and verification methodologies.</li><li>Ideally the canddate should be able to assist with the optimisation of acceleration and emulation technologies using the Cadence Incisive verification flows including the Palladium and Xtreme hardware.</li><li>The engineer must have a solid background in logic design and verification experience with Cadence technology in the digital domain.</li><li>The client should have at least a basic understanding of modeling (e.g. Architecture or system), and both block and system level verification experiance, preferably with coverage driven methodologies. </li><li>The candidate should possess the necessary engineering and consultancy skills, i.e. that he/she is technically mature with the necessary communication skills to be able to consult effectively with clients, e.g. to talk to, coach and advise Customers. </li><li>The engineer must have a solid background in the electronics industry with at least 4 to 5 years experience, and should be willing to learn new technical and consulting skills.</li></ul><span style="font-weight: bold;"><u>Key Accountabilities:</u></span><br /><ul><li>Execution on VCAD Customer support projects, e.g. Implementation and functional verification of design systems. </li><li>Development of customer specific verification environments including components, methodology support, operation and maintenance.</li><li>Be prepared to provide design and verification support in VCAD Customer design projects, both remotely and onsite.</li><li>Ability to handle all design environment implementation tasks and architectural tasks with the minimum support or through working in a joint team of Cadence and Customer engineers.</li><li>Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.</li><li>Acquire a basic understanding of the (service) business environment of Cadence within 6 months including pre sales support.</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-67485875321370498412008-10-15T00:10:00.000-07:002008-10-15T00:11:27.251-07:00DFT Engineer required for Cadence Design Systems, Bangalore<span style="font-weight: bold;"></span><span style="font-weight: bold;"><u>Experience:</u></span> 3 to 6 Years<br /><br /><span style="font-weight: bold;"><u>Location:</u></span> Bangalore, India<br /><br /><span style="font-weight: bold;"><u>Skill Sets:</u></span> Scan, Jtag, Atpg, Tester interface.<br /><br /><span style="font-weight: bold;"><u>Good to have skills:</u></span> Exposure to ATPG tools like Encounter Test<br /><br /><span style="font-weight: bold;"><u>Job Description:</u></span><br /><ul><li>This engineer’s primary role will be to work in a team oriented environment to deliver DFT activities for implementation services. He/she will interact and work with other engineers on the worldwide delivery team.</li><li>This engineer is expected to provide services using the following technical skills: Scan, JTAG, ATPG, Logic Synthesis, Static Timing Analysis, and to interface with designers / testing team.</li><li>In addition to the technical skills they will be expected to operate effectively in project teams delivering the design of leading edge. Additional responsibilities include customer interactions and pre-sales activities.</li></ul><span style="font-weight: bold;"><u>Key Accountabilities</u></span>:<br /><ul><li>Ability to handle all design environment implementation tasks assigned, either personally or through supervising other Cadence and Customer engineers.</li><li>Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.</li><li>Acquire a basic understanding of the (service) business environment of Cadence including pre sales support.</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-11911227710522878842008-06-12T22:27:00.000-07:002008-06-12T22:39:05.381-07:00Physical Design Engineer required for TechForce, Bangalore<span style="font-weight: bold;">Physical Design Engineers, Bangalore</span><br /><br /><span style="font-weight: bold;"><u>Skills:</u></span><br /><ul><li>Tools - Synopsys, Cadence, Magma tools </li><li>Technologies – 45nm, 65nm or 90nm</li></ul><strong><u>Location</u>:</strong> Hyderabad<br /><br /><strong><u>Experience</u>:</strong> 3 - 15 years experience (from Junior level to Sr Technical Lead Position)<br /><br /><strong><u>Education</u>:</strong> BE / MS / M Tech<br /><br /><span style="font-weight: bold;"><u>Job Requirements:</u></span><br /><br /><ul style="text-align: justify;"><li>Minimum 3 year of ASIC physical design experience.</li><li>Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.</li><li>Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools</li><li>Should have participated in a minimum of 3-4 fullchip tapeouts.</li><li>Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.</li><li>Familiar with Physical Verification will be a plus.</li></ul>In addition, following is desirable:<br /><ul style="text-align: justify;"><li>Effective written and oral communication skills in English</li><li>Understanding Verilog HDL</li><li>Understanding Deep Submicron effects such as 90nm and below</li><li>Understanding OCV, DFM, DFY</li><li>Excellent Block level and Fullchip level Timing closure skills</li><li>Displaying motivation, leadership skills and working in teams</li></ul><span style="font-weight: bold;"><u>Responsibilities:</u></span><br /><br /><ul style="text-align: justify;"><li>Will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks. In addition to this, will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-89394899762821351222008-04-14T02:57:00.000-07:002008-04-14T03:00:35.458-07:00Senior Verification Engineer required for TechForce Design Services<strong>Senior Verification Engineer - Bangalore</strong><br /><strong><br /><u>Skills/Expertise</u>:</strong><br /><ul><li>Language: Vera, System Verilog, System C, Verilog, VHDL</li><li>Domain: USB, PCI, PCI express, ARM, AMBA, Storage or Any peripherals </li></ul><strong><u>Location</u>:</strong> Bangalore<br /><br /><strong><u>Experience</u>:</strong> 4 yrs & above<br /><br /><strong><u>Education</u>:</strong> BE / B.Tech / ME / MTech / MS<br /><br /><strong><u>Qualification</u>:</strong><br /><strong></strong><ul><li>Expertise in either Vera language or mentioned domain expertise will be preferred</li><li>Exposure to gate level simulation (ModelSim)</li><li>Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc</li><li>Knowledge of Functional coverage using HVL language features or assertions a plus</li><li>Proficiency in developing testcases and testbench environment.</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-89587865826297911192008-04-14T02:54:00.000-07:002008-04-14T02:57:04.811-07:00Senior Verification Engineer required for TechForce Design Services<strong>Senior Verification Engineer - Hyderabad</strong><br /><p><strong><u>Skills/Expertise:</u></p><ul><li></strong>Languages: Vera, System Verilog, Verilog </li><li>Domains preferred: MPEG, MP3, Multimedia, Audio, Video</li></ul><p><strong><u>Location</u>:</strong> Hyderabad </p><strong><u>Experience</u>:</strong> 4 yrs & above<br /><br /><strong><u>Education</u>:</strong> BE / B.Tech / ME / MTech / MS<br /><p><strong><u>Qualification</u>:</strong></p><strong></strong><ul><li>Expertise in either mentioned languages or mentioned domain expertise will be preferred</li><li>Exposure to gate level simulation (ModelSim)</li><li>Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc</li><li>Knowledge of Functional coverage using HVL language features or assertions a plus</li><li>Proficiency in developing testcases and testbench environment.</li></ul><p><strong><u>Contact</u>:</strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-7397999553407401322008-04-14T02:50:00.000-07:002008-04-14T02:54:14.635-07:00ASIC Verification Engineer required for TechForce Design Services<strong>ASIC Verification Engineer - Noida</strong><br /><p><strong><u>Skills/Expertise</u>:</strong></p><ul><li>Languages: Verilog / VHDL / Specman / Vera / System Verilog / System C</li><li>Location: Noida</li></ul><strong><u>Experience</u>:</strong> 2 yrs – 8 yrs<br /><br /><strong><u>Education</u>:</strong> BE / B.Tech / ME / MTech / MS<br /><br /><strong><u>Qualification</u></strong><strong>:</strong><br /><ul><li>Experience in Verilog / VHDL / Specman / Vera / System Verilog / System C</li><li>Exposure to gate level simulation (ModelSim)</li><li>Knowledge of Code coverage using features in existing simulators or stand alone tools like Surecov, HDL score etc</li><li>Knowledge of Functional coverage using HVL language features or assertions a plus<br />Proficiency in developing testcases and testbench environment.</li></ul><p><strong><u>Important Note</u>:</strong> Free accommodation will be provided by us in Noida city until the project is completed for the selected engineers.</p><p><strong><u>Contact</u></strong>: <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a></p>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0tag:blogger.com,1999:blog-3738434149760284417.post-15737458685868355352008-04-14T02:46:00.000-07:002008-04-14T03:01:31.467-07:00ASIC Verification Engineer (Specman) required for TechForce Design Services<strong>ASIC Verification Engineer – Noida (Specman)</strong><br /><p><strong><u>Skills/Expertise:</u></strong></p><ul><li>Languages: Specman “e” </li><li>IP verification preferred </li></ul><p><strong><u>Location:</u></strong> Noida</p><p><strong><u>Experience:</u></strong> 2 yrs – 8 yrs</p><p><strong><u>Education</u></strong>: B.E. / B.Tech / ME / MTech / MS</p><p><strong><u>Qualification</u></strong>:</p><ul><li>Experience in test bench development in Specman</li><li>Experience in IP verification preferred </li><li>Experience in writing the test cases with decent debugging skills. </li></ul><p><strong><u>Important Note</u></strong>: Free accommodation will be provided by us in Noida city until the project is completed for the selected engineers.</p><strong><u>Contact:</u></strong> <a href="mailto:getjobsinindia2007@gmail.com">getjobsinindia2007@gmail.com</a>Sandeep Gorhttp://www.blogger.com/profile/17756641047106957907noreply@blogger.com0