Skills:
- Tools - Synopsys, Cadence, Magma tools
- Technologies – 45nm, 65nm or 90nm
Experience: 3 - 15 years experience (from Junior level to Sr Technical Lead Position)
Education: BE / MS / M Tech
Job Requirements:
- Minimum 3 year of ASIC physical design experience.
- Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
- Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
- Should have participated in a minimum of 3-4 fullchip tapeouts.
- Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
- Familiar with Physical Verification will be a plus.
- Effective written and oral communication skills in English
- Understanding Verilog HDL
- Understanding Deep Submicron effects such as 90nm and below
- Understanding OCV, DFM, DFY
- Excellent Block level and Fullchip level Timing closure skills
- Displaying motivation, leadership skills and working in teams
- Will be responsible for execution of Full chip floor planning and block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks. In addition to this, will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.
Contact: getjobsinindia2007@gmail.com
