Experience: 3+ years
Locaiton: Bangalore
No. of Positions: 1
Education: BE/BTech or ME/MTech
Job Requirement:
- Implementation of multimillion gate SoC designs in cutting edge process technologies (130nm, 90nm & 65nm)
- Work on all aspects of physical design including synthesis, floor planning, bond out, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout
- Clear understanding and command over all aspects of physical design
- Experience in ASIC tapeouts, preferably in 90nm or smaller technology technologies
- Expertise in Synopsys, Magma or Cadence backend tools
- Skill and experience in scripting using Tcl or Perl desirable
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