Skill/Expertise:
- Tools: Magma / Cadence / Astro
- Experience: 2 - 8 years
- Location: Hyderabad & Noida
- Education: BE – EE/EC/ET/EI
- Implementation of multimillion gate SoC designs in cutting edge process technologies (130nm, 90nm & 65nm)
- Will be working on all aspects of physical design including synthesis, floor planning, bond out, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, formal verification, DFM, and tapeout.
- Meeting highly challenging schedule, performance, and quality constraints.
- Clear understanding and command over all aspects of physical design including technology, libraries, floorplan, timing, signal integrity and power dissipation.
- Experience in ASIC tapeouts, preferably in 130nm or smaller technology nodes
- Expertise in Cadence/Magma/Astro backend tools
- Skill and experience in scripting using Tcl or Perl desirable
- Demonstrated ability to work in a team environment
Contact: getjobsinindia2007@gmail.com
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